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14–6
Table 14–5. HDL Import Block Parameters (Part 2 of 2)
Chapter 14: AltLab Library
Sort top-level
ports by name
Compile
On or Off
—
Turn on to sort the ports that the top-level HDL file alphabetically defines instead of the
order specified in the HDL.
Compiles a simulation model from the imported HDL and displays the ports defined in
the imported HDL on the block.
Figure 14–1 shows an example of an imported HDL design implementing a simple
adder with four input ports ( Input , Input1 , Input2 , sclrp ), and two output ports
( Output , Output1 ).
Figure 14–1. Typical HDL Import Block
Use std_logic_1164 types to define the input and output interfaces to the imported
VHDL. If your design uses any other VHDL type definitions (such as arithmetic or
numeric types), you should write a wrapper that converts them to std_logic or
std_logic_vector .
HDL import only supports single clock designs. If you import a design with multiple
clocks, DSP Builder uses one clock as the implicit clock and shows any others as input
ports on the Simulink block.
1
Store HDL source files in any directory or hierarchy of directories.
Table 14–6 lists the supported megafunctions and LPM functions.
Table 14–6. Supported Megafunctions and LPM Functions
Megafunctions
LPM Functions
lpm_mult
a_graycounter
altaccumulate
altmult_add
altshift_taps
altsyncram
parallel_add
scfifo
lpm_abs
lpm_add_sub
lpm_compare
lpm_counter
(1)
lpm_mux
lpm_ram_dp
Note to Table 14–6 :
(1) The lpm_mult LPM function is not supported when configured to perform a squaring operation.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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